Huawei's Tao Law Redefines Semiconductor Evolution
At the 2026 International Symposium on Circuits and Systems, Huawei's He Tingbo unveiled the 'Tao Law,' a paradigm shift from geometry-based scaling to time-based scaling (τ-scaling) that leverages logic folding to compress signal delays, aiming to sustain semiconductor advancement without relying on ever-smaller transistors. Born from U.S. tech sanctions, this strategy mandates deep co-design across algorithms, software, architecture, and chips—directly challenging the U.S.-dominated vertical division of the industry.
Under the Tao Law, Huawei has already mass-produced 381 chips, with the upcoming 2026 Kirin chip set to debut logic folding technology. The company targets achieving 1.4nm-equivalent transistor density by 2031 through systematic optimization, effectively 'trading space for time' in the post-Moore era.
The Tao Law represents a pragmatic, system-level paradigm that demonstrates how comprehensive engineering collaboration can overcome chip manufacturing bottlenecks, offering a viable path forward even as traditional geometric scaling approaches physical limits.
